A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.
Memory fault models, MBIST (Memory BIST) methods, and functional procedures.
Logic BIST basics, test pattern generation, and output response analysis. Digital System Test and Testable Design: Using ...
The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology
Scan architectures, RT-level scan design, and Boundary Scan (JTAG). A distinguishing feature is the extensive use of
Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs.
It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms. Logic BIST basics, test pattern generation, and output
This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .